CMOS image sensors are attractive for use in, e.g., still and video imaging applications, due to their compatibility with VLSI circuit design and fabrication processing. For many applications, a CMOS imager can be preferred over a corresponding CCD imager. Specifically, low-cost, large-scale CMOS design and fabrication technologies that have been developed for large-volume VLSI circuits can be directly employed in the production of CMOS imagers. CMOS imagers are, in general, much more cost effective than imagers produced based on CCD technologies.
In both CCD and CMOS imagers, imager pixels must hold, or maintain, image information produced by the pixels in the form of an electronic charge for a period of time that is typically on the order of about 10-100 milliseconds. Given this time scale, and due to the micron or submicron scale structure of CCD and CMOS pixels, any electronic leakage current generated at a pixel tends to substantially affect the image information maintained by the pixel, resulting in a distortion of the image produced by the imager.
This pixel leakage current, also referred to as “dark current,” is understood to be due to the generation of electron-hole pairs in a depletion region where pixel charge is held. Leakage current can be caused by thermally generated holes and electrons and/or by material defects in the semiconductor substrate in which the pixels are fabricated.
Thermally-produced leakage current is a fundamental phenomenon that sets the minimum leakage current which generally can be attained by state-of-the-art pixel design. Leakage current produced by material defects can, however, be addressed and is found to be design-dependent.
Leakage current produced by material defects typically results from crystal dislocations in the silicon substrate in which the pixels are fabricated. Sites of crystal dislocations act as electron-hole pair generation centers that produce a corresponding current, known as a leakage current. As a result of the leakage current, a pixel can produce an output image signal even under dim or zero illumination conditions. Thus, for any input illumination, the leakage current contribution to the pixel output distorts the image, rendering the indicated illumination brighter than the true illumination.
At a very high leakage current, the pixel output can become saturated even under zero illumination conditions. In this situation, the pixel is completely unresponsive to varying scene illumination and produces only the saturation output level. In this case, the pixel is often termed “defective” and is effectively not operative for imaging applications.
It is understood that a reduction in pixel leakage current can be obtained by the reduction in the number of the dislocations in the crystal lattice of a silicon substrate in which a pixel is fabricated. Such dislocations can be formed in the substrate, near to the substrate surface, at locations of steps between a region of thin silicon dioxide and a region of thicker silicon dioxide provided on the substrate surface. At the boundary of a thin-oxide/thick-oxide step, mechanical stress is imposed on the silicon substrate, causing crystal lattice dislocations to form in the substrate, relatively close to the substrate surface.
If a crystal lattice dislocation in the silicon substrate is formed at a substrate location that falls within the extent of a photogenerated charge sensing depletion region of a CCD or CMOS pixel, or at the location of pixel regions that are electrically connected to, and thus at the same electrical potential as the photodiode region, that dislocation can act as an electron-hole pair generation center, as explained above, producing a contribution to pixel output that is not representative of input illumination. This leakage of current distorts the electronic charge maintained by the pixel and at high current levels, renders the pixel defective.
A requirement for control of pixel leakage current has been addressed in general in conventional CCD imager fabrication technologies, with a range of design and fabrication remedies developed to reduce pixel leakage current. High performance CCD imager technologies can maintain pixel dark current to a level as low as on the order of 20-100 pA/cm2.
It is found, however, that in general, the minimum dark current obtainable by CMOS imager technologies is typically more than an order of magnitude greater than that obtainable by CCD imager technologies. In addition to being characterized by a larger average dark current than CCD imagers, CMOS imagers are in general found to be susceptible to a far larger number of defective pixels than CCD imagers.
While CCD imager technologies have been able to address the challenge of average dark current minimization and a reduction in number of defective pixels through fabrication process modifications, these CCD imager technologies require design or fabrication process modifications that are not, in general, cost effective or practical for CMOS imager technologies.
This is due to the fact that VLSI circuits produced by standard CMOS manufacturing processes, which are also employed for CMOS imagers, are largely unaffected by current leakage, and the principal advantage of CMOS imager technology is its use of such standard CMOS VLSI processing techniques. Any CMOS process modifications employed to reduce leakage current are therefore costly and inefficient, benefiting imager but not VLSI circuit applications.
The features of a CMOS pixel design layout that contribute to pixel leakage current can be illustrated with an example pixel design and corresponding fabrication layouts.
In FIG. 1, the operation of a CMOS active pixel 10 is described, using a schematic diagram of the pixel. This example pixel configuration employs a photodiode 11, but it is to be recognized that the pixel can include other light collecting configurations, embodied as, e.g., a phototransistor, a photogate, or other selected configuration.
As illustrated in FIG. 1, a photodiode 11 of the pixel produces a current of photo-generated electrical charge in response to light incident on the pixel. The resulting photocurrent is directed to a parasitic charge-sensing capacitor 13. The parasitic charge-sensing capacitor 13 is not an actual physical electrical element of a pixel, but the parasitic charge-sensing capacitor 13 represents the parasitic reverse-biased P-N junction capacitance and other parasitic capacitance associated with the photodiode 11.
A MOS transistor 15 operates as a source follower transistor that buffers the voltage on the parasitic charge-sensing capacitor 13 nondestructively to a column line 23 for read out of the voltage. Specifically, a row select MOS switch 17 activates the source follower transistor 15 when the particular row is selected, thereby enabling the parasitic charge-sensing capacitor voltage measurement. When the row select MOS switch 17 of the row is turned ON, a current source 24 is connected to the source of the MOS transistor 15. The MOS transistor 15 and the current source 24 operate as a source-follower configuration to buffer the voltage on the parasitic charge-sensing capacitor 13 to the column line 23 for determining the parasitic charge-sensing capacitor voltage at the end of an exposure period, to in effect measure the photo-generated electronic charge held by the pixel. A sense node 40 is the point in the circuit at which the parasitic charge-sensing capacitor voltage is electrically contacted for producing an output voltage to the column line 23.
FIG. 2 illustrates a top view of a conventional CMOS fabrication process layout for the pixel configuration of FIG. 1. FIG. 3 is a cross-sectional view of the conventional CMOS fabrication process layout taken at the section 3 of FIG. 2.
As illustrated in FIG. 2, the photodiode 11 is constructed between an n+ doped area 30 and a p-type substrate 41. The n+ doped area 30 acts as the cathode and the p-type substrate 41 as anode of the photodiode 11. The n+ doped area 30 is doped, typically by ion implantation, simultaneously with the doping of source and the drain areas (generally denoted as 33, 35, 37, and 39) of the NMOS transistors of the pixel.
With this configuration, the n+ cathode region of the photodiode 11 is extended out to form an n+ source 39 of the reset transistor 21 of FIG. 1. As illustrated in FIG. 2, the sense node contact 400 of the pixel is provided at the source location 39. Electrically, the n+ cathode area of the photodiode 11 as well as the source area 39 of the reset transistor 21 together form the sense node 40 of FIG. 1. The gate of the source follower transistor 15 is connected to the sense node 40 of FIG. 1 at the sense node contact point 400. The drain of the row select transistor 17 is connected to the source of the transistor 15 through n+ doped area 35.
In accordance with conventional CMOS fabrication processing, the p-type substrate 41, surrounding doped active device regions like the photodiode region 30 and the source and drain regions (33, 35, 37, and 39), is typically provided with a relatively thick silicon dioxide layer, known as the field oxide. The silicon dioxide layer in the p-type substrate 41 is about 2000-5000 in thickness.
The field silicon dioxide layer is provided with sufficient thickness to disable transistor action by polysilicon traces overlaying the oxide in their connection paths between various nodes of the transistors. In the areas forming the n+ source and drain areas, the gate areas, and the photodiode area, commonly referred to together as the “active area,” the thick field silicon dioxide layer is inhibited and in place is provided a very thin oxide layer having a thickness corresponding to the prescribed gate oxide for the transistors.
As illustrated in FIG. 3, an example of CMOS process employing shallow trench isolation technology is shown. More specifically, as illustrated in FIG. 3, a step 43 in height between the field oxide layer 42 and the thinner oxide layer 44 overlaying the active area, including the n+ photodiode area 30, is shown in cross section. Under reverse bias conditions, a depletion region 50 is formed between the n+ photodiode area 30 and the p-type substrate 41, with the depletion region 50 extending deeper into the substrate than the photodiode area due to the lower doping level in the substrate relative to the photodiode area.
Dislocations 55 tend to form in the p-type substrate 41, near to the p-type substrate's surface, at a region near to where the step 43 in oxide height is located, due to mechanical stress imposed on the p-type substrate 41 by the step 43. Such dislocations, which will typically fall in the depletion region 50, act as electron-hole pair generation centers, producing a leakage current. The leakage current contribution to the pixel output is not based on pixel illumination, but instead on a dislocation generated current.
In the pixel layout of FIG. 2, the entire perimeter of the photodiode 30 and the region of the sense node contact 400; i.e., the entire perimeter of the photodiode area 30 as well as the reset transistor source area 39, where the sense node contact 400 is made, is characterized by a step in oxide layer thickness across the boundary of these regions.
As a result of this step in the oxide layer, the entire perimeter of the photodiode area 30 as well as the reset transistor source area 39 provides a region in which dislocations can form and excessive pixel leakage current can be produced. Thus, large average dark currents and a high density of defective pixels are typically found in CMOS imagers with this pixel layout.
FIG. 4 illustrates another conventional CMOS fabrication process layout for a pixel. In FIG. 4, the photodiode area 300 is not formed by the n+ doping implantation employed for the transistor source and drain regions 33, 35, 37, and 25. Instead, the photodiode 11 is formed simultaneously with the n-type doping of n-wells produced in the substrate for forming PMOS circuits. This n-well formation is a fabrication process step separate from the n+ source and drain formation, in a conventional manner. In the configuration illustrated in FIG. 4, the sense node contact 400 is provided at the reset transistor source region 25, and the photodiode 11 and the reset transistor source are connected by extending a portion of the reset transistor source region 25 of the transistor 21 into the n-well region 300 of the photodiode 11 by forming an n+ well in the n-well region 300 of the photodiode 11.
In an example process for fabricating the configuration illustrated in FIG. 4, the photodiode area 300 is doped with the n-well doping and is thereafter covered with a thick field oxide layer along with the field surrounding the areas defined for the transistors. The regions (33, 35, 37, and 25) for defining the pixel transistors are provided with a thin gate oxide layer. A step in oxide layer height also exists across the boundaries 70 and 72 of the reset transistor source region 25 in which the sense node contact 400 is provided. This height step across the boundaries 70 and 72 of the reset transistor source region 25, where the sense node contact 400 is formed, causes dislocations and a corresponding leakage current to be produced at the sense node 40.
The average dark current of a pixel having this layout is substantially reduced compared with the pixel design of FIG. 2 because there exists no thin-thick oxide boundary along the perimeter of the n-well photodiode area 300. However, since a thick-thin oxide step does exist at the perimeter of the reset transistor source region 25, where the sense node contact 400 is provided, dislocations do exist and hence excessive leakage current and defect pixel density are not completely eliminated.
Therefore, it is desirable to provide a pixel design and corresponding fabrication process that results in a CMOS pixel imager having substantially reduced leakage current.
As discussed above, since dislocations at step regions in the oxide layer are consistent by-products of the fabrication process, it is desirable to reduce the detrimental leakage current effect of these dislocations upon a CMOS pixel; namely, the effect upon the CMOS pixel's capability to convert illumination levels into a voltage properly; without removing or decreasing the number of dislocations.
It is further desirable to reduce the detrimental leakage current effect of the dislocations produced by the fabrication process without altering the standard fabrication process. It is desirable to reduce the detrimental leakage current effect of the dislocations produced by the fabrication process without requiring additional processing steps, additional backend processes, or non-standard process sequences.
Moreover, it is desirable to mask the detrimental leakage current effect of the dislocations produced by the fabrication process. Lastly, it is desirable to reduce the detrimental leakage current effect of the dislocations produced by the fabrication process by using a standard CMOS fabrication process that has not been modified with expensive fabrication steps.